1. Technical Field
The present invention relates to a pulse generator and, more particularly, to a pulse generator using a latch for generating a pulse to sequentially latch input data applied to a source data line of a liquid crystal display device.
2. Discussion of Related Art
Liquid crystal display (LCD) devices are used widely in, for example, notebook computers and monitors. In an LCD device a controlled electric field is applied to a liquid crystal (LC) material having an anisotropic dielectric constant, disposed between two panels to control light transmission for displaying an image.
Conventional LCD devices include two panels for implementing an image and have a plurality of pixels. The plurality of pixels is disposed in an area in which a plurality of scan lines applying gate selection signals intersect a plurality of source data lines applying color data, e.g., grayscale data.
To latch the color data for the individual source data lines of the LCD device with a conventional latching circuit, a series of latch signal pulses is generated and applied in sequence. A plurality of pulse generators is connected in series, with each pulse generator producing a latch signal pulse for latching color data and a next data signal pulse for operating the next pulse generator in the series. The pulse generators are triggered by the same, substantially square wave, system clock so the intervals and durations of the pulses are uniform. A start pulse is generated based on the clock and is, for example, a high logic level pulse with a duration of about one cycle of the clock. The start pulse can begin and end on subsequent edges of the clock, such as rising edges.
In a first pulse generator of the series of pulse generators, the start pulse is input as a data signal to a first latching device, such as a flip-flop, and is latched into the first latching device on an opposite edge of the clock from the start pulse, such as a falling edge, so the logic level of the start pulse that began on a rising edge of the clock is stable by the time the falling edge of the clock occurs. The start pulse is at a low logic level by the time the next falling edge of the clock latches the first latching device. The two latching operations causes a high logic level first pulse that is one clock cycle in duration and one half clock cycle delayed from the start pulse. The resulting first pulse is used as a first one of the series of latch signals and is also used with a second latching device to produce a next data signal in a similar manner. The first pulse is input as a data signal to the second latching device and is latched into the second latching device on the same rising edge of the clock that ended the start pulse. The first pulse is at a low logic level by the time the next rising edge of the clock latches the second latching device. The two latching operations of the second latching device causes a high logic level second pulse that is one clock cycle in duration, one half clock cycle delayed from the first pulse, and one clock cycle delayed from the start pulse. The resulting second pulse is used as the data signal to the first latching device of the next pulse generator in the series of pulse generators.
In the series of pulse generators, each pulse generator produces a latch signal pulse that is one clock cycle in duration and one clock cycle delayed from the latch signal pulse of the previous pulse generator, and a next data signal pulse that is one clock cycle in duration and one clock cycle delayed from the next data pulse of the previous pulse generator. If a start pulse has a multiple clock cycle duration, then the resulting latch pulses may also have a multiple clock cycle duration. There may be as many pulse generators in the series as there are source data lines in a section of or in the entire LCD device.
FIG. 1 is a circuit diagram of a conventional pulse generator using flip-flops. As illustrated in FIG. 1, each pulse generator 10 includes a first flip-flop 11 and a second flip-flop 12 for latching a data signal A and for generating a latch pulse CLK and a next data signal NEXT_DIN in response to a predetermined clock signal SH_CLK. The first flip-flop 11 has a data input D, an inverted clock input CKB, a reset input RN, and a latched output Q. The second flip-flop 12 has a data input D, a clock input CK, a reset input RN, and a latched output Q. Each flip-flop 11 and 12 is reset by a low logic level of a predetermined reset signal RSTB applied to the reset inputs RN. The first flip-flop 11 receives a start signal SR_START at the data input D and latches a logic level of the start signal SH_START, such as a high logic level, through the latched output Q as latch signal CLK in response to a falling edge of a predetermined clock signal SH_CLK at the inverted clock input CKB of the first flip-flop 11. The latched output Q of the first flip-flop 11 is reset in response to a next falling edge of the predetermined clock signal SH_CLK when the start signal SH_START changes logic levels, such as to a low logic level.
The latch signal CLK from the latched output Q of the first flip-flop 11 is in the form of a pulse and is used to latch the color data applied to one of the source data lines of the LCD device.
The latch signal CLK is also applied to the data input D of the second flip-flop 12, and latches a logic level of the latch signal CLK, such as a high logic level, through the latched output Q of the second flip-flop 12 as a next data signal NEXT_DIN in response to a rising edge of the predetermined clock signal SH_CLK at the clock input CK of the second flip-flop 12. The latched output Q of the second flip-flop 12 is reset in response to a next rising edge of the predetermined clock signal SH_CLK when the latch signal CLK changes logic levels, such as to a low logic level.
The next data signal NEXT_DIN from the latched output Q of the second flip-flop 12 is applied as the data signal A to a next pulse generator (not shown) connected in series with the pulse generator 10.
FIG. 2 is a block diagram of a series of the conventional pulse generators of FIG. 1. As illustrated in FIG. 2, each pulse generator 10-1 to 10-n has a start signal input A, which is the data input D of the first flip-flop 11, a latch signal output CLK, which is the latched output Q of the first flip-flop 11, and a next start signal output NEXT_DIN, which is the latched output Q of the second flip-flop 12. Second through last pulse generators 10-2 to 10-n have next start signals NEXT_DIN from the previous pulse generators 10-1 to 10-n-1 applied to their start signal inputs A, respectively. The first pulse generator 10-1 in the series has the start signal SH_START applied to its start signal input A. The next start signal output NEXT_DIN of the last pulse generator 10-n is unused.
The first through last latch signal outputs CLK of the first through last pulse generators 10-1 to 10-n are applied to the LCD device as latch enable signals CLK1 to CLKn to latch the color data applied to the plurality of source data lines.
FIG. 3 is a timing diagram illustrating operations of the pulse generators of FIGS. 1 and 2. The timing chart illustrated in FIG. 3 relates to a case in which a color data signal is input to 240 data lines crossing a row in an LCD device. When a synchronization signal HSYNC indicating an input cycle for a row of color data signals is enabled, the first and second flip-flops 11 and 12 are reset, and the start signal SH_START is sent to the data input D of the first flip-flop 11 of the first pulse generator 10-1.
The logic level of the start signal SH_START is latched at the latched output Q of the first flip-flop 11 of the first pulse generator 10-1 in response to a failing edge of the predetermined clock signal SH_CLK, and a latched output CLK from the output terminal Q of the first flip-flop 11 is output as first latch signal CLK1 from the first pulse generator 10-1 in the form of a pulse and is used for latching color data sent to the first source data line. The latched output Q CLK of the first flip-flop 11 is applied to the second flip-flop 12 and is output from the latched output Q of the second flip-flop 12 in response to a rising edge of the predetermined clock signal SH_CLK.
A latched output signal NEXT_DIN of the second flip-flop 12 is applied as an input to the next pulse generator connected in series to the pulse generator 10. A flip-flop included in the next pulse generator receives the output signal NEXT_DIN and applies an output signal CLK2 in response to a falling edge of the clock signal SH_CLK. Accordingly, the output signals CLK1 and CLK2 generated by the adjacently connected pulse generators have a phase difference of one cycle of the clock signal SH_CLK between each other. Accordingly, data SH_DATA:[17:0] for a pixel is transmitted to the source data line during a cycle of the clock signal SH_CLK.
An enable signal ENABLE illustrated in FIG. 2 is a control signal controlling the transmission of data signals to a pixel implementing an image. The timing chart of the enable signal ENABLE shows an operation of transmitting grayscale data PD[17:0] to the pixel in response to a predetermined clock signal DOTCLK during an active period of the enable signal ENABLE.
However, in a conventional pulse generator using flip-flops as described above, since there is energy consumption in gates to which a clock signal is applied whenever the clock signal toggles, as the number of pulse generators increases, the number of gates accordingly increases. Thus, more space is occupied and unnecessary electric power is consumed.